Difference between l1,l2,l3

what is cache?
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations. As long as most memory accesses are cached memory locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main memory.
When the processor needs to read from or write to a location in main memory, it first checks whether a copy of that data is in the cache. If so, the processor immediately reads from or writes to the cache, which is much faster than reading from or writing to main memory.
The diagram on the right shows two memories. Each location in each memory has a datum (a cache line), which in different designs ranges in size from 8[1] to 512[2] bytes. The size of the cache line is usually larger than the size of the usual access requested by a CPU instruction, which ranges from 1 to 16 bytes. Each location in each memory also has an index, which is a unique number used to refer to that location. The index for a location in main memory is called an address. Each location in the cache has a tag that contains the index of the datum in main memory that has been cached. In a CPU's data cache these entries are called cache lines or cache blocks.
Most modern desktop and server CPUs have at least three independent caches: an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, and a translation lookaside buffer used to speed up virtual-to-physical address translation for both executable instructions and data.

what is l1,l2,l3
L1 cache is physically next to the processing core and is implemented in SRAM, or Static RAM which is fast and constant when powered on. It does not require refresh cycles. It is generally split with half used for instruction code and the the other used for data.
L2 cache is physically close to the core, but is implemented in DRAM or Dynamic RAM and goes through refresh cycles many time a second to retain its memory. It is not as fast as L1 and cannot be accessed during refresh.
L3 cache has come into vogue with the advent of multi-core CPUs. Whereas these chips will have both L1 and L2 caches for each separate core; there is a common fairly large L3 shared by all cores. It is usually the size of all other caches combined or a few multiples of all other caches combined. It is also implemented in DRAM. One unusual thing is that a multi-core chip that is running software that may not be capable of or need all cores will have a core flush its caches into the L3 before that core goes dormant